AD9833 DDS Reference for a 12–18 MHz PLL Oscillator

This homebrew project is a 160–40 meter SSB/CW transceiver. It has a PLL with an AD9833 DDS reference. As in most modern transceivers, the design allows 1.5 Hz resolution, low noise, and flexible frequency management. The photo below shows the control unit. It has an Atmel microprocessor and a 128 × 64 pixel graphic display. The circuit board above it holds the VCO, the PLL, and the 10.7 MHz IF receiver with a tunable crystal filter (0.5–3 kHz bandwidth).

The heart of my 160–40 m transceiver is the PLL. The AD9833 DDS is the reference oscillator. The VCO frequency is divided by a factor of 16. The result is compared with the output frequency of the AD9833 DDS in the 74HC4046 phase/frequency comparator. The output signal of the phase comparator is filtered by a low-pass filter built around a TL071 operational amplifier. The resulting output voltage drives the BB201 varactor diode of the VCO. The AD9833 was chosen because of its low supply current of only 5 mA.

See the circuit diagram of the PLL here (PDF).